1. Field of the Invention
The present invention relates to a three layered polishing pad and a method for polishing and planarizing irregular surfaces, such as semiconductor wafers.
2. Background of the Invention
Semiconductor wafers are cut from ingots of single crystal silicon which are formed by withdrawing a seed from a silicon melt rotating in a crucible. The ingot is then sliced into individual wafers using a diamond cutting blade. Following the cutting operation, at least one surface of the wafer is polished to a relatively flat, scratch-free surface. Due to manufacturing irregularities, however, the thickness of the wafers equally vary. For example, the thickness of six inch wafers may range from 0.650 to 0.700 mm. Furthermore, the thickness of each wafer may vary by as much as 3.0 um across the wafer.
In the manufacture of integrated circuit semiconductor devices, the polished surface area of the wafer is first subdivided into a plurality of locations at which integrated circuits (IC) are formed. A series of wafer masking and processing steps are used to fabricate each IC. Thereafter, the individual ICs are cut or scribed from the wafer and individually packaged and tested to complete the device manufacture process.
The masking and processing steps during fabrication may result in the formation of topographical irregularities on the wafer surface. For example, topographical surface irregularities are created after metallization, which includes the sequence of blanketing the wafer surface with a conductive metal layer and then etching away unwanted portions of the blanket metal layer to form a metallization interconnect pattern on each IC.
The height differential (h) between the metal interconnect and the wafer surface where the metal has been removed results in a wafer surface irregularity commonly referred to as a step. On a very large-scale integrated (VLSI) IC, the step features can average 1 um or more in height and have a lateral surface dimension ranging from approximately 1 um to more than 1 mm. A typical VLSI chip on which a first metallization layer has been defined may contain several million steps, and the whole wafer may contain several hundred ICs.
Referring to FIG. 1, a perspective view of a processed semiconductor wafer 10 is shown. The wafer 10 includes a plurality of ICs 12. Each IC 12 includes a center region 14 which usually includes a high degree of device integration, and an outer periphery region 16 which typically has a relatively lower degree of device integration. Each IC is separated from the other ICs by scribe lines 18.
Referring to FIG. 2, a cross section of the wafer of FIG. 1 taken along line 2'--2' is shown. The cross sectional view of the wafer 10 illustrates several characteristics which are typically found on a wafer after Metallization. First, the thickness of the wafer is not uniform. The center region 30 of the wafer 10 has a thickness of T.sub.1 which is thicker than the peripheral regions 32 of the wafer having a thickness T.sub.2. It should be noted that wafer 10 is merely illustrative, and that the regions at which the thickness of the wafer may vary may occur at different portions of the wafer.
Second, a higher percentage of the center regions 14 of each IC 12 are elevated due to the high degree of device integration in these regions. In contrast, a substantially lower percentage of the peripheral regions 16 of each IC are lower with respect to the center regions 14 due to the lower degree of device integration. Hereinafter, the center regions 14 and peripheral regions 16 are referred to as high density regions 14 and low density regions 16 respectively.
Third, the high degree of device integration in the high density regions 14 creates a large number of steps 34 on the surface of the wafer. The gaps between each step 34 in the high density regions 14 generally have a lateral dimension of one micron or less. In contrast, the low degree of device integration in the low density regions 16 creates a relatively smaller number of steps 34 in these regions. The gaps between steps in the low density regions 16 may range from 1 micron to one millimeter, and the gaps between two high density regions 14 may range from 0.5 to 3.0 millimeters in lateral dimension. (Note, the thickness disparity (T.sub.1 vs. T.sub.2), the height and lateral dimensions of the steps 34, and the gaps between the steps relative to the dimensions of the wafer are greatly exaggerated for clarity.)
Fourth, a dielectric layer 19, such as silicon dioxide, is deposited over the wafer surface by a chemical deposition or another known technique. The dielectric layer 19 assumes the same topography as the underlying wafer surface.
Referring to FIG. 3, an exploded view of a high density region 14 between lines 3'--3' of the cross section of the wafer 10 of FIG. 2 is shown. This exploded cross section view illustrates that wafer topography irregularities are also created by trench isolation, which is common technique used in VLSI circuits to prevent latch up and to increase device density. The exploded cross section view of FIG. 3 includes an n-channel device 40 and a p-channel device 42 built in an n-well 43 in wafer 10. A dielectric trench 44 separates devices 40 and 42 in the substrate 10. A first metallization layer 45 electrically couples devices 40 and 42. Dielectric layer 19 covers the top surface of the devices 40 and 42 and the topography of the wafer above the trench 44 is raised above the remainder of the wafer surface.
The lack of planarization due to metallization and trench isolation on the wafer surface can cause significant problems during wafer fabrication. For example, the steps 34 on the high density and low density regions 14 and 16 respectively may cause focusing problems during optical lithography. Since the dielectric layer 19 which is deposited over the wafer surface after metallization and trench isolation assumes the irregularities of the wafer surface, the lack of surface planarization may make it difficult or impossible to lay down subsequent layers of metal interconnect, thus limiting the number of metallization layers that can be practically used in device manufacture.
Polishing the dielectric layer 19 on the surface of a wafer after metallization and/or other selected stages in the fabrication process is one known method for planarizing wafer surface topography. Since the dielectric layer 19 covers the surface of the wafer, it provides a layer of uniform composition for planarization.
Referring to FIG. 4, a cross section of a standard wafer polishing apparatus is shown. The polishing apparatus 20 includes a platen 21 for supporting a polishing pad 23, a wafer chuck 24 having side walls 25a and 25b and a resilient pad 2 6. The back of the unprocessed surface 27 of a wafer 10 rests against resilient pad 26 and is positioned by side walls 25a and 25b in wafer chuck 24. The processed surface 28 of the wafer is thus in contact with and exposed to the polishing pad 23 during operation.
The platen 21 rotates about a first axis 29a. The wafer chuck 24 and wafer 10 rotate about a second axis 29b which is substantially in parallel with axis 29a. A member 61 moves the rotating wafer chuck 24 horizontally across the surface of the polishing pad 23. As wafer 10 is rotated, its processed surface 28 moves across the polishing surface of the polishing pad 23.
During operation, a slurry of colloidal silica or another suitable abrasive is introduced between the dielectric layer on the wafer 10 and the polishing pad 23. The reaction between the slurry and the dielectric layer under the polishing motion results in the chemical-mechanical removal of the dielectric on the wafer surface. Ideally, the dielectric material would be typically removed faster over the high density regions 14 than in the low density regions 16 on the wafer surface. Thus, the topography of the wafer surface would be polished and planarized. In actuality, less than ideal results are obtained using polishing pads known in the art today.
Referring to FIG. 5, a two-layered polishing pad according to the prior art is shown. The pad 36 includes a resilient layer 37 and a polishing layer 38 covering the resilient layer. When placed in contact with a processed surface of the wafer, the polishing layer maintains contact with the high density regions 14. The polishing layer 38 bridges the gaps in the high density regions 14 since lateral distance of the gaps in the high density regions 14 are in the order of 1 micron.
The resilient layer 37 however forces the polishing layer 38 into the low density regions 16 so that the polishing layer 38 conforms to the local topography of the low density regions 16.
The two-layered polishing pad 36 has a number of deficiencies. The materials for the polishing layer 38 known in the art, such as urethane, are not rigid enough, causing the polishing layer 38 to conform generally to the low density regions 16 and to any gaps which are greater than approximately 1 mm in lateral dimension. As a result, the rate at which the polishing pad 36 removes dielectric material from the high density and low density regions 14 and 16, respectively, or any gaps with a lateral dimension of 1 mm or greater, is substantially equal. Accordingly, the pad of FIG. 5 has a leveling length, which is defined as the lateral distance over which the pad will maintain its rigidity over a local portion of the wafer, of approximately 1 mm, which is too short and does not result in the planarization of the wafer surface.
The lack of rigidity of the polishing pad 36 also results in the uneven rate of dielectric material removal over regions of different device integration density. Since the polishing force in both high density and low density regions are substantially equal, the polishing pressure applied to the low density regions is greater than the polishing pressure in the high density regions because there is less surface area of the polishing pad in contact with the wafer topography in the low density regions. As a result, the dielectric material is removed faster in the low density regions 16. The uneven removal rate may lead to excess removal of the dielectric layer 19 on the wafer surface, which may destroy the underlying devices.
Furthermore, the polishing layer performs the dual role of polishing the wafer surface and providing a rigidity to the polishing surface of the pad. Therefore, the mechanical properties of the two layer pad are vulnerable to change due to wear and use of the pad. The two layered polishing pad thus exhibits changes over time in its ability to planarize. This is undesirable because the mass production of wafers requires consistency.
Published European patent application, No. 0223920, discloses a method of polishing semiconductor wafers using a chemical-mechanical polishing technique with an improved polishing slurry. The polishing pad material is made of a polyester material is firm enough so that it does not deform under the polishing load.
Semiconductor manufacturers also use other methods for wafer planarization, such as spin on glass (SOG). In the SOG procedure, a sacrificial layer of glass is spun onto the dielectric layer 19. Ideally, the glass flows and fills in the low density regions 16 and gaps prior to curing. Thereafter, the glass layer and dielectric layer 19 are etched back at the same rate, leaving behind a planar wafer surface.
The SOG technique also has major deficiencies. First, the glass is only capable of filling gaps up to approximately 40 microns. Gaps of 40 microns or greater are only partially filled by the glass. Second, the etch rates of the glass and the dielectric are not identical. Accordingly, the larger gaps such as the low density regions 16 remain unfilled and therefore are not level with the high density regions 14, and the surface remains non-planar after etch back.
The failure of prior art planarization techniques significantly reduces chip yields and greatly increases IC manufacturing costs. The failure to planarize the wafer surface limits the number of subsequent metallization layers that can be used to build the ICs on the wafer. Lastly, a non-planar wafer surface limits the critical dimension, which is defined as the smallest feature of on the wafer surface, such as the geometrical gate length, which can be fabricated on the wafer surface. Smaller feature sizes require a lithography tool with a shallower depth of field and this requires better planarization of the wafer surface.